1. Technical Field
The present invention relates to a semiconductor device in which memory cells comprising a plurality of MISFETs (metal-insulator-semiconductor FETs) are arranged in at least one dimension.
2. Background Art
The layout of a prior art memory cell matrix array 1 is shown in FIGS. 7-10. Memory cell matrix array 1 comprises a ROM (read-only memory) and is disposed on a semiconductor device 2. The information stored in the memory cell matrix array 1 is read out relative to activated word lines WL connected with a row decoder 3.
FIG. 8 shows the electrical circuit equivalent of memory cell matrix array 1. In matrix array 1, m N-channel MIS transistors 10 arranged along word lines WL constitute one row. N-channel MIS transistors 10 are arranged in parallel n rows. Thus, matrix array 1 comprises n rows and m columns. Word lines WL1-WLn are connected to the gates of the N-channel MIS transistors 10 of these rows. The drains of the N-channel MIS transistors 10 of each column are connected with respective bit lines BL1-BLm. The sources of the N-channel MIS transistors 10 of each row are common with the adjacent N-channel MIS transistors 10 of the same column. Power supply lines VL are connected to the transistor sources. As an example of operation, information stored in a particular N-channel MIS transistor (x, y) is caused to appear on a bit line BLy if the particular transistor (x, y) is activated by the word line WLx of the x.sup.th row.
FIG. 9 particularly shows an enlarged end portion identified at IX in FIG. 7 of memory cell matrix array 1. In the fabrication of memory cell matrix array 1, first p-type wells 20 are formed in a semiconductor substrate. Then, the active regions of the N-channel MIS transistors are determined and defined relative to their sources, drains and channel regions. Also, channel stop regions are determined. In the next step, a nitride film is formed over the entire surface of the substrate and patterned employing an element-separation mask, except relative to the transistor active regions. Then, boron is implanted into the laminate to increase the density of the p-type dopant. Then, the laminate is thermally treated at a high temperature for a long period of time. Consequently, the surfaces of the channel stop regions are oxidized excluding the transistor active regions 21 which are not protected by the nitride film.
In the next step, after the formation of the oxide film, the nitride film on transistor active regions 21 is removed to form a gate oxide film and and defined gate electrodes 22, such as, gate electrodes 22a, 22b, 22c shown in FIG. 10. Gate electrodes 22 function as a mask for the implantation of phosphorus into the transistor active regions 21 forming an n-type layer. In this manner, N-channel MIS transistors 30 are formed at the intersections of the active regions 21 and the gate electrodes 22.
Gate electrodes 22 (22a, 22b, 22c) are arranged horizontally to form rows as shown in FIG. 9. These rows constitute the word lines WL shown in FIG. 8. Transistor active regions 21 are parallel to gate electrodes 22, and form an n-type layer constituting sources 23 (23a, 23b, 23c) of N-channel MIS transistors 30. Active regions 21 of the n-type layer, which are located on opposite sides of gate electrodes 22 from sources 23 (23a, 23b, 23c) of N-channel MIS transistors 30, form drains 24 (24a, 24b, 24c) of N-channel MIS transistors 30. Sources 23 are common with N-channel MIS transistors 30 which are associated with gate electrodes 22 formed on the opposite side of sources 23. As an example, source 23b forms the sources of the N-channel MIS transistors 30d-30i associated with gate electrodes 22b and 22c. Drains 24 are common with N-channel MIS transistors 30 located on the opposite sides of the drains. For example, drain 24b forms the drains of N-channel MIS transistors 30b and 30e located on the opposite sides of drain 24b.
Attention is now directed to the ends of transistor active regions 21 forming the memory cells as previously described. Some end portions are illustrated in FIG. 10 and each consists of the active region forming sources 23a of N-channel MIS transistors 30a-30c and the active region forming the channels and the drains of N-channel MIS transistors 30a, 30d, 30g. These active regions are narrowed compared with other active regions. It is considered that various causes are responsible for these decreases in width in the active region, such as, thermal shrinkage of the resist on separation of the elements and instability of the flow of gas around the outer edge during the etching process. In any case, this phenomenon is inevitable to appear at the boundaries between the elements patterned at a high density and their surroundings patterned at a lower density, as in the case of a memory cell matrix array.
In manufacturing practice of forming transistor active regions 21, active regions indicated at cross-hatched regions 32 in FIG. 10 are reduced in dimension for transistor active regions 31 shown in FIG. 10. For this reason, the N-channel MIS transistors formed along the outer edge of the memory cell array are inferior in performance compared to the N-channel MIS transistors formed within the memory cell array. For example, the active regions of N-channel MIS transistors 30a, 30d, and 30g formed along one end of the memory cell array are narrowed. Consequently, the channels in these N-channel MIS transistors are narrower than their intended design. In N-channel MIS transistors 30a, 30b, 30c where the transistor active regions forming the sources are narrowed, the resistance of the sources is increased. Therefore, the access time to N-channel MIS transistors 30a-30d and 30g is larger than the intended access time. It follows, therefore, that the access time to the memory cell matrix array is governed by the access time to the N-channel MIS transistors formed in these marginal portions of the memory cell array.
If a margin is added to the width of each transistor active region in order to obtain the intended access time to the N-channel MIS transistors formed along the outer edge, then the inner transistor active regions become excessively large reducing the packing density of the memory cells. Also, the parasitic capacitance in the N-channel MIS transistors is increased, because the distances among the memory cells are increased. Hence, the access time is increased to the memory cell matrix array.